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RTC2RTMP: fix illegal memory access. v7.0.97 (#4520)

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Regression since 20f6cd595c

The early code might meet bridge is empty when
there is no bridge(e.x. rtc to rtc). Then srs_freep will free the brige.

Remove this code that seems redundant.

---------

Co-authored-by: Jacob Su <suzp1984@gmail.com>
Signed-off-by: Jack Lau <jacklau1222@qq.com>
This commit is contained in:
Jack Lau 2025-10-15 22:16:03 +08:00 committed by GitHub
parent 44c3dab79e
commit 6f526284a3
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GPG Key ID: B5690EEEBB952194
4 changed files with 13 additions and 17 deletions
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1
trunk/doc/CHANGELOG.md
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@ -7,6 +7,7 @@ The changelog for SRS.
<a name="v7-changes"></a>
## SRS 7.0 Changelog
* v7.0, 2025-10-15, Merge [#4520](https://github.com/ossrs/srs/pull/4520): srs_app_rtc_conn: fix illegal memory access. v7.0.97 (#4520)
* v7.0, 2025-10-14, Disable sanitizer by default to fix memory leak. (#4364) v7.0.96
* v7.0, 2025-10-01, SRT: Support configurable default_streamid option. v7.0.95 (#4515)
* v7.0, 2025-09-27, Merge [#4513](https://github.com/ossrs/srs/pull/4513): For Edge, only support RTMP or HTTP-FLV. v7.0.94 (#4513)

5
trunk/src/app/srs_app_rtc_conn.cpp
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@ -1310,11 +1310,6 @@ srs_error_t SrsRtcPublishStream::initialize(ISrsRequest *r, SrsRtcSourceDescript
return srs_error_wrap(err, "create bridge");
}
if ((err = bridge->initialize(r)) != srs_success) {
srs_freep(bridge);
return srs_error_wrap(err, "create bridge");
}
source_->set_bridge(bridge);
return err;

2
trunk/src/core/srs_core_version7.hpp
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@ -9,6 +9,6 @@
#define VERSION_MAJOR 7
#define VERSION_MINOR 0
#define VERSION_REVISION 96
#define VERSION_REVISION 97
#endif

22
trunk/src/utest/srs_utest_app17.cpp
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@ -4556,12 +4556,12 @@ VOID TEST(CircuitBreakerTest, InitializeAndWaterLevelTransitions)
// Configure circuit breaker settings
mock_config->circuit_breaker_enabled_ = true;
mock_config->high_threshold_ = 90; // CPU > 90% triggers high water level
mock_config->high_pulse_ = 2; // High level lasts for 2 timer ticks
mock_config->critical_threshold_ = 95; // CPU > 95% triggers critical water level
mock_config->critical_pulse_ = 1; // Critical level lasts for 1 timer tick
mock_config->dying_threshold_ = 99; // CPU > 99% triggers dying water level
mock_config->dying_pulse_ = 5; // Dying level requires 5 consecutive ticks
mock_config->high_threshold_ = 90; // CPU > 90% triggers high water level
mock_config->high_pulse_ = 2; // High level lasts for 2 timer ticks
mock_config->critical_threshold_ = 95; // CPU > 95% triggers critical water level
mock_config->critical_pulse_ = 1; // Critical level lasts for 1 timer tick
mock_config->dying_threshold_ = 99; // CPU > 99% triggers dying water level
mock_config->dying_pulse_ = 5; // Dying level requires 5 consecutive ticks
// Create SrsCircuitBreaker
SrsUniquePtr<SrsCircuitBreaker> breaker(new SrsCircuitBreaker());
@ -4584,7 +4584,7 @@ VOID TEST(CircuitBreakerTest, InitializeAndWaterLevelTransitions)
EXPECT_FALSE(breaker->hybrid_dying_water_level());
// Test 3: Simulate high CPU load (91% > high_threshold 90%)
mock_host->proc_stat_->percent_ = 0.91; // 91% CPU
mock_host->proc_stat_->percent_ = 0.91; // 91% CPU
HELPER_EXPECT_SUCCESS(breaker->on_timer(1 * SRS_UTIME_SECONDS));
// After 1 tick with high CPU, high water level should be active
@ -4593,7 +4593,7 @@ VOID TEST(CircuitBreakerTest, InitializeAndWaterLevelTransitions)
EXPECT_FALSE(breaker->hybrid_dying_water_level());
// Test 4: Simulate critical CPU load (96% > critical_threshold 95%)
mock_host->proc_stat_->percent_ = 0.96; // 96% CPU
mock_host->proc_stat_->percent_ = 0.96; // 96% CPU
HELPER_EXPECT_SUCCESS(breaker->on_timer(1 * SRS_UTIME_SECONDS));
// After 1 tick with critical CPU, both high and critical should be active
@ -4603,7 +4603,7 @@ VOID TEST(CircuitBreakerTest, InitializeAndWaterLevelTransitions)
// Test 5: Simulate dying CPU load (99.5% > dying_threshold 99%)
// Need 5 consecutive ticks to activate dying level
mock_host->proc_stat_->percent_ = 0.995; // 99.5% CPU
mock_host->proc_stat_->percent_ = 0.995; // 99.5% CPU
for (int i = 0; i < 5; i++) {
HELPER_EXPECT_SUCCESS(breaker->on_timer(1 * SRS_UTIME_SECONDS));
}
@ -4614,7 +4614,7 @@ VOID TEST(CircuitBreakerTest, InitializeAndWaterLevelTransitions)
EXPECT_TRUE(breaker->hybrid_dying_water_level());
// Test 6: Simulate CPU load decrease (back to 50%)
mock_host->proc_stat_->percent_ = 0.50; // 50% CPU
mock_host->proc_stat_->percent_ = 0.50; // 50% CPU
HELPER_EXPECT_SUCCESS(breaker->on_timer(1 * SRS_UTIME_SECONDS));
// Dying level should immediately reset to 0 when CPU drops
@ -4627,7 +4627,7 @@ VOID TEST(CircuitBreakerTest, InitializeAndWaterLevelTransitions)
// Test 7: Continue with low CPU - high should decay to 0 after 1 more tick
HELPER_EXPECT_SUCCESS(breaker->on_timer(1 * SRS_UTIME_SECONDS));
EXPECT_FALSE(breaker->hybrid_high_water_level()); // High now false (high_water_level_ = 0)
EXPECT_FALSE(breaker->hybrid_high_water_level()); // High now false (high_water_level_ = 0)
EXPECT_FALSE(breaker->hybrid_critical_water_level());
EXPECT_FALSE(breaker->hybrid_dying_water_level());