From 6f526284a3370a5c6c9dd8ccedf2e6bb8fac3ec4 Mon Sep 17 00:00:00 2001 From: Jack Lau <2366536135@qq.com> Date: Wed, 15 Oct 2025 22:16:03 +0800 Subject: [PATCH] RTC2RTMP: fix illegal memory access. v7.0.97 (#4520) Regression since 20f6cd595cc8be63a824d29d1332abd4488685be The early code might meet bridge is empty when there is no bridge(e.x. rtc to rtc). Then srs_freep will free the brige. Remove this code that seems redundant. --------- Co-authored-by: Jacob Su Signed-off-by: Jack Lau --- trunk/doc/CHANGELOG.md | 1 + trunk/src/app/srs_app_rtc_conn.cpp | 5 ----- trunk/src/core/srs_core_version7.hpp | 2 +- trunk/src/utest/srs_utest_app17.cpp | 22 +++++++++++----------- 4 files changed, 13 insertions(+), 17 deletions(-) diff --git a/trunk/doc/CHANGELOG.md b/trunk/doc/CHANGELOG.md index 5233bccdd..b3efba63b 100644 --- a/trunk/doc/CHANGELOG.md +++ b/trunk/doc/CHANGELOG.md @@ -7,6 +7,7 @@ The changelog for SRS. ## SRS 7.0 Changelog +* v7.0, 2025-10-15, Merge [#4520](https://github.com/ossrs/srs/pull/4520): srs_app_rtc_conn: fix illegal memory access. v7.0.97 (#4520) * v7.0, 2025-10-14, Disable sanitizer by default to fix memory leak. (#4364) v7.0.96 * v7.0, 2025-10-01, SRT: Support configurable default_streamid option. v7.0.95 (#4515) * v7.0, 2025-09-27, Merge [#4513](https://github.com/ossrs/srs/pull/4513): For Edge, only support RTMP or HTTP-FLV. v7.0.94 (#4513) diff --git a/trunk/src/app/srs_app_rtc_conn.cpp b/trunk/src/app/srs_app_rtc_conn.cpp index 2c596e058..8c60942dd 100644 --- a/trunk/src/app/srs_app_rtc_conn.cpp +++ b/trunk/src/app/srs_app_rtc_conn.cpp @@ -1310,11 +1310,6 @@ srs_error_t SrsRtcPublishStream::initialize(ISrsRequest *r, SrsRtcSourceDescript return srs_error_wrap(err, "create bridge"); } - if ((err = bridge->initialize(r)) != srs_success) { - srs_freep(bridge); - return srs_error_wrap(err, "create bridge"); - } - source_->set_bridge(bridge); return err; diff --git a/trunk/src/core/srs_core_version7.hpp b/trunk/src/core/srs_core_version7.hpp index 628d9d10c..8148205a2 100644 --- a/trunk/src/core/srs_core_version7.hpp +++ b/trunk/src/core/srs_core_version7.hpp @@ -9,6 +9,6 @@ #define VERSION_MAJOR 7 #define VERSION_MINOR 0 -#define VERSION_REVISION 96 +#define VERSION_REVISION 97 #endif \ No newline at end of file diff --git a/trunk/src/utest/srs_utest_app17.cpp b/trunk/src/utest/srs_utest_app17.cpp index 940395373..4e4adac4f 100644 --- a/trunk/src/utest/srs_utest_app17.cpp +++ b/trunk/src/utest/srs_utest_app17.cpp @@ -4556,12 +4556,12 @@ VOID TEST(CircuitBreakerTest, InitializeAndWaterLevelTransitions) // Configure circuit breaker settings mock_config->circuit_breaker_enabled_ = true; - mock_config->high_threshold_ = 90; // CPU > 90% triggers high water level - mock_config->high_pulse_ = 2; // High level lasts for 2 timer ticks - mock_config->critical_threshold_ = 95; // CPU > 95% triggers critical water level - mock_config->critical_pulse_ = 1; // Critical level lasts for 1 timer tick - mock_config->dying_threshold_ = 99; // CPU > 99% triggers dying water level - mock_config->dying_pulse_ = 5; // Dying level requires 5 consecutive ticks + mock_config->high_threshold_ = 90; // CPU > 90% triggers high water level + mock_config->high_pulse_ = 2; // High level lasts for 2 timer ticks + mock_config->critical_threshold_ = 95; // CPU > 95% triggers critical water level + mock_config->critical_pulse_ = 1; // Critical level lasts for 1 timer tick + mock_config->dying_threshold_ = 99; // CPU > 99% triggers dying water level + mock_config->dying_pulse_ = 5; // Dying level requires 5 consecutive ticks // Create SrsCircuitBreaker SrsUniquePtr breaker(new SrsCircuitBreaker()); @@ -4584,7 +4584,7 @@ VOID TEST(CircuitBreakerTest, InitializeAndWaterLevelTransitions) EXPECT_FALSE(breaker->hybrid_dying_water_level()); // Test 3: Simulate high CPU load (91% > high_threshold 90%) - mock_host->proc_stat_->percent_ = 0.91; // 91% CPU + mock_host->proc_stat_->percent_ = 0.91; // 91% CPU HELPER_EXPECT_SUCCESS(breaker->on_timer(1 * SRS_UTIME_SECONDS)); // After 1 tick with high CPU, high water level should be active @@ -4593,7 +4593,7 @@ VOID TEST(CircuitBreakerTest, InitializeAndWaterLevelTransitions) EXPECT_FALSE(breaker->hybrid_dying_water_level()); // Test 4: Simulate critical CPU load (96% > critical_threshold 95%) - mock_host->proc_stat_->percent_ = 0.96; // 96% CPU + mock_host->proc_stat_->percent_ = 0.96; // 96% CPU HELPER_EXPECT_SUCCESS(breaker->on_timer(1 * SRS_UTIME_SECONDS)); // After 1 tick with critical CPU, both high and critical should be active @@ -4603,7 +4603,7 @@ VOID TEST(CircuitBreakerTest, InitializeAndWaterLevelTransitions) // Test 5: Simulate dying CPU load (99.5% > dying_threshold 99%) // Need 5 consecutive ticks to activate dying level - mock_host->proc_stat_->percent_ = 0.995; // 99.5% CPU + mock_host->proc_stat_->percent_ = 0.995; // 99.5% CPU for (int i = 0; i < 5; i++) { HELPER_EXPECT_SUCCESS(breaker->on_timer(1 * SRS_UTIME_SECONDS)); } @@ -4614,7 +4614,7 @@ VOID TEST(CircuitBreakerTest, InitializeAndWaterLevelTransitions) EXPECT_TRUE(breaker->hybrid_dying_water_level()); // Test 6: Simulate CPU load decrease (back to 50%) - mock_host->proc_stat_->percent_ = 0.50; // 50% CPU + mock_host->proc_stat_->percent_ = 0.50; // 50% CPU HELPER_EXPECT_SUCCESS(breaker->on_timer(1 * SRS_UTIME_SECONDS)); // Dying level should immediately reset to 0 when CPU drops @@ -4627,7 +4627,7 @@ VOID TEST(CircuitBreakerTest, InitializeAndWaterLevelTransitions) // Test 7: Continue with low CPU - high should decay to 0 after 1 more tick HELPER_EXPECT_SUCCESS(breaker->on_timer(1 * SRS_UTIME_SECONDS)); - EXPECT_FALSE(breaker->hybrid_high_water_level()); // High now false (high_water_level_ = 0) + EXPECT_FALSE(breaker->hybrid_high_water_level()); // High now false (high_water_level_ = 0) EXPECT_FALSE(breaker->hybrid_critical_water_level()); EXPECT_FALSE(breaker->hybrid_dying_water_level());